It is often required to synthesize a signal source having a frequency which is a rational factor n/m times an existing reference or clock frequency. This need for synthesis may include cases where n and m are relatively prime large integers and typical implementation of such synthesizers involves the use of phase locked loops (“PLL”) operating on prescaled (divided) frequency versions of the desired signal and the reference or clock signal. These PLL synthesizers typically use a comparison frequency that is m times smaller than the reference or clock signal and thus produce synthesized signals on the desired frequency but with phase noise limitations due to large frequency divisions associated with large values of m. In such applications, the phase noise power is proportional to the square of the division ratio.
It is the object of the instant invention to provide for a synthesizer that permits rational synthesis, i.e. synthesis of a signal source having a frequency which is a rational factor n/m times an existing reference or clock frequency, without incurring phase noise degradations thereby providing for a signal source with phase noise essentially equal to that of the reference signal.